The present invention relates generally to an input/output execution apparatus for a plural-OS run system in which a plurality of operating systems or OSs are allowed to run on a bare machine. More particularly, the invention is concerned with an input/output execution apparatus which is capable of executing a plurality of input/output (I/O) instructions and input/output (I/O) interrupts having an achitecture of the bare machine and/or other architectures differing from that of the bare machine.
As a typical example of a system which is designed to allow a plurality of operating systems (OSs) to run on a single computer, there is mentioned a logical partitioned system disclosed in JP-A-64-37636 and a virtual machine system. In the data processing system disclosed in the publication mentioned above, a single computer resource is logically partitioned so as to be made available by each of the plurality of OSs with a view to allowing the OS to execute the input/output interrupt processing at a high speed. This known logical partitioned system is characterized in that hardware including microcodes controls the runs of the plural OSs. Thus, such a control program as required by a virtual machine system is rendered unnecessary in the case of the logical partitioned system.
In JP-A-62-31437 corresponding to U.S. patent application Ser. No. 890,524 filed on Jul. 13, 1986 in the name of S. Tanaka et al. now U.S. Pat. No. 4,887,202, there is disclosed a virtual machine system in which input/output instructions issued by an OS on a virtual machine and input/output interrupts to an OS on a virtual machine are directly or straightforwardly executed by the hardware.
With the virtual machine system (hereinafter referred to simply as "VMS"), it is intended to mean a system which makes it possible for a plurality of logical machines, i.e. virtual machines (hereinafter referred to as `VM`) to simultaneously run on a single real computer. Recently, such a system has been developed and reported in which both a VM of a 370-XA architecture having an addressing mechanism of 31 bits and a VM of a S/370 architecture having an addressing mechanism of 24 bits can simultaneously run on a real computer of the 370-XA architecture, as is described, for example, in "IBM System/370 Extended Architecture Interpretive Execution SA-22-7095". For more particulars of the architectures 370-XA and S/370, reference may be made to "370-XA Principles Of Operation SA-22-7085" and "S/370 Principles Of Operation GA-22-7000", respectively. Parenthetically, these architectures 370-XA and S/370 correspond, respectively, to the M/EX and M architectures in the M-series general purpose computers commercially available from Hitachi Ltd. of Japan.
The architectures S/370 and 370-XA of the machines described in the literatures cited above or the architectures M/EX and M of the M-series general purpose computers differ from each other in respect to the format for the input/output instruction and the input/output interrupt in addition to the addressing mechanisms. Under these circumstances, the input/output instruction and the input/output interrupt of the VM are simulated with the aid of a virtual machine control program (hereinafter referred to as `VMCP`). However, the simulation of the input/output instruction and the input/output interrupt by the VMCP takes a lot of time, lowering the processing speed, because the simulation is performed by employing a program to this end.
In view of the situation mentioned above, and for the purpose of reducing the overhead involved in the input/output simulation, there has been proposed a method of directly executing the input/output processings of the VM all by hardware as disclosed in, for example, JP-A-60-150140 corresponding to U.S. patent application Ser. No. 691,909 filed Jan. 16, 1985 in the name of H. Umeno et al. now U.S. Pat. No. 4,885,681 which is incorporated herein by reference. In this publication, a method is disclosed for executing directly the input/output instruction and the input/output interrupt of a VM of the M/EX-mode on a hardware basis in a real computer of M/EX architecture, which will be described below in detail by reference to several figures of the accompanying drawings.
FIGS. 18 to 22 of the accompanying drawings are views for elucidating operation of a direct input/output (I/O) execution system, wherein FIG. 18 is a block diagram showing generally a functional structure of a computer of the M/EX architecture.
The computer is composed of a main storage 1000, a central processing unit (CPU) 2000, an input/output processor (IOP) 3000, an input/output controller (IOC) 4000 and an input/outout (I/O) device 5000. The IOC and the I/O device are shown as single devices for the convenience of description, although each of these devices is provided in multiplicity in practical applications. The main storage 1000 stores therein an I/O execution request queue 1100, an I/O interrupt request queue 1200, an address translation table 1300 for the IOP, an area for a number of subchannels 1400 corresponding to the number of the I/O devices and a SD region 1500 for a number of state descriptions (SD) corresponding to that of the VMs. The state description or SD holds a register value of VM and assumes the initial value thereof upon activation of the VM, as is described in the literature entitled "IBM System 370 Extended Architecture Interpretive Execution" mentioned hereinbefore. The CPU 2000 includes an instruction register 2100 for storing the instruction read out from the main storage 1000, an instruction decoder 2110 for decoding the instruction, an instruction executing circuit 2120 for executing the instruction, a host interrupt activating circuit 2210 for deciding whether or not the VMCP is capable of interruption, an interrupt processing circuit 2300 for performing the interrupt processing and a variety of control registers such as an IE-mode bit register 2400, a host PSW register 2410 and a host CR6 register 2420 provided in association with the VMCP, and a guest PSW register 2430 and a guest CR6 register 2440 provided in association with the VM.
In the following, operation of the computer system having the structure outlined above will be described with regard to (i) environment setting or establishing processing, (ii) VM activation processing, (iii) execution of I/O instruction of VM and (iv) execution of I/O interrupt to VM in this order.
(i) Environment setting processing for direct I/O execution
FIG. 19 of the accompanying drawings is a view for illustrating the relation existing between a real main storage of a real computer and the main storages of the VMs together with the contents of the address translation table for the IOP.
In the exemplary case shown in FIG. 19, the objective (object) for the direct I/O execution is a VM of a resident storage mode (also represented by V=Resident VM) in which the main storage (level-2 memory) 1000-1 of the VM exists on the real main storage (level-1 memory) with displacement of .alpha..sub.i (i=1, 2, . . . ). Accordingly, the address translation table 1300 for translating the address of level 2 to that of level 1 is first prepared. The address translation table 1300 for the IOP is of such a structure that a set of an origin address .alpha..sub.i and an end address .alpha..sub.i+1 of the main storage of VM on the real storage 1000 can be determined from a region identifier (RID) identifying the VM. In the case of the system disclosed in JP-A-60-150140 mentioned hereinbefore, the objective for the direct input/output (I/O) execution is the I/O device dedicated only to a VM of concern. Accordingly, in the processing for the dedication of the I/O device to the VM, the VMCP sets to "1" a subchannel direct I/O flag (SCH-DIO) 1410 of the subchannel 1400 corresponding to the I/O device of concern while setting a region identifier RID of the dedicatee VM at a subchannel region identifier (SCH-RID) so that the CPU 2000 can discriminatively identify the dedicated state of the I/O device. The region identifier RID is identical with the corresponding RID of the address translation table 1300 for the IOP which is affixed to the main storage of the dedicatee VM to which the I/O device is dedicated (refer to FIG. 19).
(ii) VM activation processing
A SIE (Start Interpretive Execution) instruction which is the instruction for activating a VM has as an operand the address of the SD (state description) 1500 of the main storage 1000 shown in FIG. 18. The SD 1500 includes a SD-DIO 1510 for indicating the direct input/output execution when the content thereof is "1", an RID set at the region identifier in state description (SD-RID) 1520 for allowing the CPU to identify the running VM, and a state description architecture identifier (SD-ARCH) 1530 for allowing the CPU to identify the architecture (i.e. M/EX or M) of the running VM. More specifically, when the SD-ARCH identifier 1530 is "0", this means that the running VM is in the M mode while identifier 1530 of "1" indicates that the VM is in the M/EX mode. It should be mentioned that the SD-DIO (direct I/O execution flag in state description) 1510, the SD-RID 1250 and the SD-ARCH 1530 are set by the VMCP and cannot be modified by hardware.
Upon the issuance of the SIE instruction, the instruction execution circuit 2120 sets "1" at the interpretive execution (IE) mode bit 2400, indicating that the VM is running, while the values of the host PSW and CR6 of the VMCP are set at the host PSW 2410 and the host control register CR6 2420, respectively, with the values of the guest resister stored in the SD 1500 corresponding to the VM being set at the guest PSW 2430 and the guest CR6 2440, respectively. However, an I/O mask realized by the bit 6 of the host PSW 2410 is placed with bit 6 of the guest PSW 2430. Further, dedication of interrupt subclass (also referred to simply as subclass) is a prerequisite for the direct execution of the input/output interrupt. To this end, when the VMCP allows a real subclass 1 to be dedicated to a VM1 and when the real subclass 1 corresponds to a virtual subclass 0,
(a) the bit 1 of the host CR6 2420 (i.e. the mask of the real subclass 1) is placed with "0", if the mask value of the virtual subclass is "0", i.e. if the bit 0 of the guest CR6 2440 is "0", and
(b) the bit 1 of the host CR6 2420 is placed with "1", if the mask value of the virtual subclass 0 is "1".
Through the processing described above, it is possible to make a decision for the subclass dedicated to a running VM as to the allowableness of an interrupt to a VM with the aid of the I/O mask of the host PSW 2410 and the mask of the host CR6 2420.
(iii) Execution of I/O instruction of VM
The input/output activation instruction issued by the running VM of the M/EX-mode is executed by the instruction execution circuit 2120 in the manner described below.
(a) The instruction execution circuit 2120 makes access to the SD-DIO 1510 of the SD 1500, wherein when the SD-DIO 1510 is "1", a next step (b) is executed. Otherwise, execution of the instruction is prohibited or suppressed, whereon the instruction execution circuit 2120 intercepts the instruction and transfers it to the VMCP.
(b) The instruction execution circuit 2120 makes access to the subchannel designated by the instruction. When the SCH-DIO 1410 is "1" and when the SCH-RID 1420 is in coincidence with the SD-RID 1520, execution proceeds to the next step (c). Otherwise, execution of the instruction is suppressed, and the circuit 2120 intercepts the instruction and transfers it to the VMCP.
(c) Subsequently, the instruction execution circuit 2120 calculates the address of a second operand (B.sub.2 /D.sub.2) and locates the input/output information stored at the calculated address in a predetermined region in the corresponding subchannel 1400.
(d) In case the subchannel is in the state ready for executing the input/output operation (i.e. when the channel and the IOC 4000 leading to the corresponding input/output device 5000 are free or vacant), the input/output execution is performed while adding the origin address .alpha..sub.i of the relevant VM stored in the IOP address translation table 1300 corresponding to the SCH-RID 1420 to the data address and CCWs address of a group of virtual channel command words (CCW) (see FIG. 19) on the level-2 memory prepared by the OS by the address translation circuit 3100 incorporated in the IOP 3000. On the other hand, unless the subchannel 1400 is in the state ready for the input/output execution (i.e. when the channel or IOC is busy), the subchannel 1400 is queued in an I/O execution request queue 1100 shown in FIG. 20. When the subchannel and the IOC become vacant or free, the IOP 3000 performs a reactivation processing for the input/output execution request queued in the I/O execution queue 1100.
In this way, the input/output instruction to the device dedicated to the running VM is directly or straightforwardly executed by hardware without intervention of the VMCP.
(iv) Execution of I/O interrupt to VM
It is assumed that the subchannel 1400 is placed in correspondence relation with the virtual subclass 0, i.e. the real subclass 1 which is an interrupt subclass for the direct input/output execution. In that case, the value of the I/O mask of the guest PSW 2430 coincides with that of the I/O mask of the host PSW 2410 and additionally the value of the bit 0 corresponding to the virtual subclass 0 of the guest CR6 2420 is in coincidence with that of the bit 1 which corresponds to the real subclass 1 of the host CR6. Thus, for the subchannel 1400 to which the virtual subclass 0 is allocated, the interrupt enabling condition in the host coincides with the interrupt enabling condition in the guest. The interrupt of the subchannel 1400 is executed in a manner described below.
(a) When an interrupt request takes place in the subchannel 1400, the IOP 3000 places the subchannel 1400 in an I/O interrupt request queue 1200 (see FIG. 21) for the subclass 1 represented by the real subclass number which is set in the subchannel 1400.
(b) Subsequently, the IOP 3000 sets to "1" the bit 1 (corresponding to the real subclass 1) of a real interrupt suspending or reserving register 2214 incorporated in the host interrupt activation circuit 2210 shown in FIG. 22.
(c) Assuming that the bit 1 of the host CR6 2420 is "1", then the output of the AND circuits 2211 corresponds to the subclass 1 assumes "1" with the output of an OR circuit 2212 also being "1". Further, when the value of the I/O mask of the host PSW 2410 is "1", the output of an AND circuit 2213 is "1", whereby an activation signal is sent to the interrupt processing circuit 2300.
(d) In the interrupt processing circuit 2300, the leading subchannel 1400 of the I/O interrupt request queue 1200 for the relevant subclass is dequeued, whereon the interrupt code stored in the subchannel 1400 is placed in a predetermined region of a prefix save area (PSA) of the VM. The PSA is an area for storing interface information between the software and hardware, wherein the start address for the interrupt processing routine or the like information is stored at the predetermined address. Further, the guest PSW 2430 at the time of interruption is saved in an I/O OLD PSW field in the PSA of the VM, while a new PSW for the I/O interrupt in the PSA of VM is loaded in the guest PSW 2430, being followed by execution of the instruction, whereupon the interrupt processing comes to an end.
As will be appreciated from the foregoing description, for the subclass for direct input/output execution which is dedicated to a running VM, interruption to the VM is executed only when it is possible. On the other hand, in case the VM is in the state not ready for interrupting on the subclass for the direct input/output execution upon occurrence of an interrupt request, the subchannel 1400 is queued in the relevant one of the I/O interrupt request queues 1200.
The system described in JP-A-60-150140 is certainly effective for reducing significantly overhead involved in the input/output processing of the VM of the resident storage mode. However, this conventional technology system suffers from the four problems, as described be low.
(a) The first problem relates to the input/output interrupt. More specifically, because the I/O mask of the guest PSW 2430 is set by the I/O mask of the host PSW 2410 during the running of the OS, there arises such a situation arises in which the I/O interrupt to the other OS or host is undesirably prohibited when the I/O mask of the guest PSW 2430 is "0". With the term "host", it is intended to indicate a plural-OS control hardware means in the case of a system as in the logical partition system in which a plurality of OSs can run on a single computer under the control of the plural-0S control hardware means. In a virtual machine system, the "host" means a VMCP.
(b) The second problem relates to the machine architecture. More specifically, in the case of the system described in JP-A-60-150140, the direct input/output execution of the OS of M/EX architecture is performed under the control of the real computer of a M/EX mode. However, the situation arises in which the direct I/O execution of the OS the of M mode should desirably be performed efficiently under the control of the real computer of the M/EX architecture. For coping with this problem, there is disclosed in JP-A-62-108335 corresponding to a U.S. Pat. No. 4,814,975 a system in which the input/output instruction issued by an OS on a VM is once intercepted and transferred to the VMCP, whereon the VMCP reissues the instruction by designating the architecture of the above-mentioned VM. Thus, the intercept and transfer of the instruction issued by the OS on the VM to the VMCP and simulation by the VMCP lead to overhead.
In JP-A-63-3342, there is disclosed a system in which upon issuance of the input/output execution request of a VM or occurrence of the input/output interrupt request to a VM, the architecture of the VM is determined based on the VM identifier to thereby perform the input/output processing which conforms to the architecture of the VM. However, also in this system, the processing for determining the architecture of the VM presents overhead. It should further be pointed out that the publication mentioned above discloses no teaching concerning how to decide whether the VM is capable of input/output interrupt.
In JP-A-58-191046, there is disclosed a system in which a real computer of S/370-mode executes directly the input/output instruction of a VM of the same architecture S/370 and the input/output interrupt to a VM of the same architecture S/370.
Further, disclosed in JP-A-60-83168 is a real computer of the 370/XA-mode in which the input/output instruction of a VM of the S/370-mode and the input/output interrupt to a VM of the S/370-mode are simulated by a VMCP (referred to as partitioned multiple processing program PMP in this publication).
Additionally, JP-A-60-57438 discloses a virtual machine system controller in which a plurality of different microprograms are prepared for one computer, wherein a corresponding microprogram is selected for each of the VMs for executing an instruction, to thereby allow an OS having an architecture different from that of the bare machine to run. However, the teaching of this publication is concerned only with the microprograms in an instruction processing unit and thus can not be applied to the OS input/output instruction and the input/output interrupt which relate to the input/output processing operation and the input/output interrupt operation, respectively.
In JP-A-58-20066, there is disclosed a method and a virtualizer system in which a plurality of virtual machines each equivalent to a bare machine are generated, wherein correspondence is established between a virtual resource simulated on a general purpose host computer and a real process executed by the host computer. However, this hardware virtualizer is not inputted with the architectures of the virtual machines. Consequently, it is impossible to process the input/output instruction of the OS and the input/output interrupt to the OS on the virtual machine in accordance with the architecture thereof.
(c) The third problem is seen in conjunction with the I/O interrupt processing which ends abnormally. More specifically, when the input/output operation to a device dedicated to a given OS has ended abnormally due to channel error, it is desirable to inform a host of this interrupt to thereby make the host perform the recovery processing for removing the channel error. In other words, in case the input/output operation has ended in a particular state, it is desirable not to interrupt directly the OS but to inform the host of this fact, because then the reliability of the input/output operation of other OS executed by other input/output device under the same channel can be enhanced by the recovery processing performed by the host. However, in the system disclosed in the publication mentioned just above, it is impossible to inform the host of the input/output interrupt ended in the particular state.
(d) The fourth problem relates to the execution of load control instruction of the guest CR6. More specifically, in order to execute directly the input/output interrupt to an OS, it is necessary that hardware can determine the condition for enabling the input/output interrupt to the OS. Accordingly, when the OS has altered or modified the guest CR6, the hardware has to process the interrupt in accordance with the interrupt enabling condition indicated by the altered guest CR6. However, due to the absence of the translating means for translating the virtual subclass number to the real subclass number in the conventional systems mentioned above, it is impossible to execute efficiently the load control instruction of the guest CR6 without intercepting the host.